1. Field of the Invention
The present invention relates to packaging substrates and methods of fabricating the same, and, more particularly, to a packaging substrate having an embedded through-via interposer for carrying a semiconductor chip and a method of fabricating the same.
2. Description of Related Art
FIG. 1 is a schematic cross-sectional view of a conventional flip-chip package structure. In fabrication, a bismaleimide-triazine (BT) packaging substrate 10 that has a core board 102, a first surface 10a and a second surface 10b is provided, and a plurality of flip-chip bonding pads 100 are formed on the first surface 10a of the packaging substrate 10; the flip-chip bonding pads 100 are electrically connected to conductive lands 120 of a semiconductor chip 12 through a plurality of solder bumps 11; then, an underfill 17 is applied to fill the gap between the first surface 10a of the packaging substrate 10 and the semiconductor chip 12 for encapsulating the solder bumps 11; and the second surface 10b of the packaging substrate 10 has a plurality of solder pads 101 so as for solder balls 13 to be mounted thereon and electrically connect the solder pads 101 to another electronic device such as a printed circuit board (not shown).
To improve the electrical performance of the semiconductor chip 12, a dielectric material having an extreme low k (ELK) or an ultra low k (ULK) is usually used in a back-end of line (BEOL) of the semiconductor chip 12. However, such a low-k dielectric material is porous and brittle. Therefore, during a thermal cycling test for reliability characterization of the flip-chip packaging structure, the solder bumps 11 easily crack due to uneven thermal stresses caused by a significant difference between the thermal expansion coefficients (CTE) of the packaging substrate 10 and the semiconductor chip 12, thereby easily causing the semiconductor chip 12 to crack and hence reducing the product reliability.
Further, along with the development of thin-profiled and compact-sized electronic products having a variety of functions, the semiconductor chip 12 has to have a high density of nano-scale circuits and thus reduced pitches between the conductive lands 120. However, the flip-chip bonding pads 100 of the packaging substrate 10 are of micro-scale pitches, which do not match the high-density nano-scale circuits of the semiconductor chip 12.
Therefore, there is a need to provide a packaging substrate and a method of fabricating the same so as to overcome the above-described drawbacks.